1. Field of the Invention
This invention relates to processors and, more particularly, to execution of floating-point arithmetic instructions.
2. Description of the Related Art
In many processor implementations that include support for floating-point arithmetic, support for conversion of data from an integer format to a floating-point format is also provided. For example, an instruction set architecture may define specific instructions to perform such conversion, in order to allow programmers to perform floating-point operations on data originally formatted as integer data.
In some embodiments, floating-point data is represented in a normalized format in which the floating-point mantissa and exponent are adjusted so that the most significant bit of the floating-point mantissa is equal to one. If the result of a floating-point operation, such as addition or subtraction, is not normalized, a normalization shift may be performed to normalize the result. Additionally, in some embodiments certain floating-point results may not be capable of an exact representation using a finite number of digits. In some such embodiments, such inexact results may be rounded according to a particular rounding mode.
When floating-point operands are normalized, it may be the case that a given floating-point addition or subtraction operation requires either a large normalization shift of the result or result rounding, but not both. In some embodiments, a floating-point addition pipeline may be optimized for the exclusivity of these cases, for example by allowing normalization and rounding to occur in parallel rather than serially.
However, integer data that is to be converted to floating-point format is not necessarily normalized, and may not exactly convert to floating-point representation (thus requiring rounding). Integer-to-floating-point conversion may therefore violate the exclusivity assumption just mentioned. In some embodiments, if integer-to-floating-point conversion is implemented within a floating-point addition pipeline that is optimized based on the exclusivity of normalization and rounding, integer-to-floating-point conversion instructions may require an extra execution cycle relative to other floating-point instructions in order to perform rounding. This may degrade performance of the conversion instructions and may create a pipeline hazard in pipelined floating-point embodiments, which may degrade the performance of other floating-point instructions. In an alternative embodiment, additional dedicated logic may be implemented specifically to handle normalization of integer operands, but such additional logic may incur additional design area and power consumption.